1. Field of the Invention
This invention is related to the field of memory controllers.
2. Description of the Related Art
Memory controllers are designed to interface to various types of memory, on behalf of one or more requesters (e.g. processors, peripheral devices, etc.). Typically, the memory controller is designed to provide certain latency and bandwidth characteristics. In general, it is desirable to provide low latency and high bandwidth access to memory. However, it is frequently the case that optimizations made to reduce latency may reduce the bandwidth. Similarly, it is frequently the case that optimizations made to increase the bandwidth lead to increased latency. Thus, the designer must often make choices between low latency features and high bandwidth features in designing a memory controller.
The latency and bandwidth characteristics of a given memory controller may be selected, e.g., based on the expected workload of the memory controller. For example, memory controllers may often be optimized for processor accesses, in which latency is often the key characteristic. Other types of workloads may favor bandwidth over latency. For example, in networking environments, large numbers of packets may be written to and read from memory. While low latency for such accesses is desirable, having high bandwidth may be more important to ensure that the packets can be written to and read from memory without having to drop packets, or without slowing down the network packet traffic with flow control.
A memory controller that may be used in implementations for which low latency is more important (e.g. processor workloads) and in implementations for which high bandwidth is more important (e.g. packet processing workloads) presents challenges to the designer when selecting the appropriate bandwidth and latency characteristics, especially if the features implemented to improve one characteristic may cause degradation in the other characteristic. Similarly, memory controller implementations which may have large workloads of both types present such challenges.